x86: Support more than 256 pins of ioapic.

Some large system may have many ioapics which
have more than 256 pins totally. To support this
case, just let pirq == irq and build 1:1 mapping
between them, and this is based on the assumpation
that pirq == GSI number in dom0 for iopaic IRQs.

Thank Jan Beulich from Novell for reporting the issue
in pv_ops dom0.

Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>

diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 8d7edf0eaac7e1afeb46ee9dc3b269afa19e4f23..47f324c276b484cd4da27b4a6613b107dd36d68c 100644 (file)
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -2193,12 +2193,14 @@ int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val)
     desc = irq_to_desc(irq);
     cfg = desc->chip_data;
 
-    /* Since PHYSDEVOP_alloc_irq_vector is dummy, rte.vector is the pirq
-       which corresponds to this ioapic pin, retrieve it for building
-       pirq and irq mapping. 
+    /*
+     * Since PHYSDEVOP_alloc_irq_vector is dummy, rte.vector is the pirq
+     * which corresponds to this ioapic pin, retrieve it for building
+     * pirq and irq mapping. Where the GSI is greater than 256, we assume
+     * that dom0 pirq == irq.
      */
-    pirq = rte.vector;
-    if(pirq < 0 || pirq >= dom0->nr_pirqs)
+    pirq = (irq >= 256) ? irq : rte.vector;
+    if ( (pirq < 0) || (pirq >= dom0->nr_pirqs) )
         return -EINVAL;
     
     if ( desc->action )